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LM5025B www.ti.com snvs354b ? july 2005 ? revised march 2013 LM5025B active clamp voltage mode pwm controller check for samples: LM5025B 1 features description the LM5025B is a functional variant of the lm5025 2 ? internal start-up bias regulator active clamp pwm controller. the functional ? 3a compound main gate driver differences of the LM5025B are as follows: ? programmable line under-voltage lockout ? the maximum pwm duty cycle is limited to less (uvlo) with adjustable hysteresis than 75% to reduce voltage stress on the power mosfets. ? voltage mode control with feed-forward ? the cs2 hiccup mode threshold is increased to ? adjustable dual mode over-current protection 0.5v ? programmable overlap or deadtime between ? the cs2 filter discharge device is disabled the main and active clamp outputs ? the v cc regulator continues to operate when the ? volt x second maximum duty cycle clamp line uvlo is below the threshold of normal ? programmable soft-start operation ? current sense leading edge blanking ? the v ref regulator is switched off when the line uvlo input falls below the operating threshold ? single resistor programmable oscillator ? the internal 5k ? comp pin pull-up resistor is ? oscillator up / down sync capability removed ? precision 5v reference the LM5025B pwm controller contains all of the ? thermal shutdown features necessary to implement power converters utilizing the active clamp / reset technique. with the packages active clamp technique, higher efficiencies and ? tssop-16 greater power densities can be realized compared to conventional catch winding or rdc clamp / reset ? wson-16 (5x5 mm) thermally enhanced techniques. two control outputs are provided, the main power switch control (out_a) and the active clamp switch control (out_b). the two internal compound gate drivers parallel both mos and bipolar devices, providing superior gate drive characteristics. this controller is designed for high-speed operation including an oscillator frequency range up to 1mhz and total pwm and current sense propagation delays less than 100ns. the LM5025B includes a high-voltage start-up regulator that operates over a wide input range of 13v to 100v. additional features include: line under voltage lockout (uvlo), softstart, oscillator up/down sync capability, precision reference and thermal shutdown. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2005 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
LM5025B snvs354b ? july 2005 ? revised march 2013 www.ti.com typical application circuit figure 1. simplified active clamp forward power converter connection diagram figure 2. 16-lead tssop (see package number pw0016a) 16-lead wson (see package number nhq0016a) 2 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM5025B ramp cs1 cs2 time ref v cc out_a v in rt comp ss agnd pgnd out_b sync uvlo 14 13 12 11 10 8 9 15 16 1 2 3 4 5 7 6 LM5025B uvlo pgnd agnd comp out_a out_b v cc ss rt sync ref time ramp cs1 v in v in 35 - 78v v out 3.3v up/down sync error amp & isolation cs2
LM5025B www.ti.com snvs354b ? july 2005 ? revised march 2013 pin descriptions pin name description application information 1 v in source input voltage input to start-up regulator. input range 13v to 100v, with transient capability to 105v. 2 ramp modulator ramp signal an external rc circuit from vin sets the ramp slope. this pin is discharged at the conclusion of every cycle by an internal fet, initiated by either the internal clock or the v*sec clamp comparator. 3 cs1 current sense input for cycle-by-cycle limiting if cs1 exceeds 0.25v the outputs will go into cycle-by- cycle current limit. cs1 is held low for 50ns after out_a switches high providing leading edge blanking. 4 cs2 current sense input for soft restart if cs2 exceeds 0.5v the outputs will be disabled and a softstart commenced. the soft-start capacitor will be fully discharged and then released with a pull-up current of 1 a. after the first output pulse (when ss =1v), the ss charge current will revert back to 20 a. 5 time output overlap/deadtime control an external resistor (r set ) sets either the overlap time or dead time for the active clamp output. an r set resistor connected between time and gnd produces in-phase out_a and out_b pulses with overlap. an r set resistor connected between time and ref produces out-of-phase out_a and out_b pulses with deadtime. 6 ref precision 5 volt reference output maximum output current: 10ma locally decouple with a 0.1 f capacitor. reference stays low until the v cc uv comparator and line uvlo comparator are satisfied. 7 v cc output from the internal high voltage start-up if an auxiliary winding raises the voltage on this pin above regulator. the v cc voltage is regulated to 7.6v. the regulation setpoint, the internal start-up regulator will shutdown, reducing the ic power dissipation. 8 out_a main output driver output of the main switch pwm output gate driver. output capability of 3a peak sink current. 9 out_b active clamp output driver output of the active clamp switch gate driver. capable of 1.25a peak sink current.. 10 pgnd power ground connect directly to analog ground. 11 agnd analog ground connect directly to power ground. 12 ss soft-start control an external capacitor and an internal 20 a current source set the soft-start ramp. the ss current source is reduced to 1ua following a cs2 over-current event or an over temperature event. 13 comp input to the pulse width modulator pwm duty cycle is controlled by the voltage applied to the comp pin. the comp pin voltage is reduced by a fixed 1v offset and compared with the ramp pin signal. 14 rt oscillator timing resistor pin an external resistor connected from rt to ground sets the internal oscillator frequency. 15 sync oscillator up/down synchronization input the internal oscillator can be synchronized to an external clock with a frequency 20% lower than the internal oscillator ? s free running frequency. there is no constraint on the maximum sync frequency. 16 uvlo line under-voltage shutdown an external voltage divider from the power source sets the shutdown comparator levels. the comparator threshold is 2.5v. hysteresis is set by an internal current source (20 a) that is switched on or off as the uvlo pin potential crosses the 2.5v threshold. - ep exposed pad, underside of the wson package internally bonded to the die substrate. connect to gnd option potential with low thermal impedance. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: LM5025B
LM5025B snvs354b ? july 2005 ? revised march 2013 www.ti.com block diagram figure 3. simplified block diagram 4 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM5025B v in ref ss 20 p a rt logic pgnd agnd 5v reference oscillator clk cs1 time 0.25v 0.5v pwm 1v r s q q ss ff ramp cs2 ramp slope d v in clk + leb 7.6v series regulator out_b driver v cc comp ss ss amp (sink only) max v*s clamp sync 2.5v + - uvlo + - out_a driver v cc v cc v cc uvlo 2.5v 19 p a deadtime or overlap control + - + - + - enable outputs and ref uvlo hysteresis (20 p a)
LM5025B www.ti.com snvs354b ? july 2005 ? revised march 2013 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. absolute maximum ratings (1) (2) v in to gnd -0.3v to 105v v cc to gnd -0.3v to 16v cs1, cs2 to gnd -0.3 to 1.00v all other inputs to gnd -0.3 to 7v esd rating (3) human body model 2kv storage temperature range -55 c to 150 c junction temperature 150 c (1) absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions under which operation of the device is intended to be functional. for specifications and test conditions, see the electrical characteristics. (2) if military/aerospace specified devices are required, please contact the texas instruments sales office/ distributors for availability and specifications. (3) for detailed information on soldering plastic tssop and wson packages, refer to the packaging data book visit www.ti.com/packaging . operating ratings (1) v in voltage 13 to 100v external voltage applied to v cc 8 to 15v operating junction temperature -40 c to +125 c (1) absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions under which operation of the device is intended to be functional. for specifications and test conditions, see the electrical characteristics. electrical characteristics (1) specifications with standard typeface are for t j = 25 c, and those with boldface type apply over full operating junction temperature range . v in = 48v, v cc = 10v, rt = 26.7k ? , r set = 27.4k ? ) unless otherwise stated symbol parameter conditions min typ max units startup regulator v cc reg v cc regulation no load 7.3 7.6 7.9 v v cc current limit (2) 20 25 ma i-v in startup regulator v in = 100v 165 500 a leakage (external vcc supply) v cc supply v cc under-voltage v cc reg - v cc reg - v lockout voltage (positive 220mv 120mv going v cc ) v cc under-voltage 1.0 1.5 2.0 v hysteresis v cc supply current (i cc ) c gate = 0 4.2 ma reference supply v ref ref voltage i ref = 0 ma 4.85 5 5.15 v ref voltage regulation i ref = 0 to 10ma 25 50 mv ref current limit 10 20 ma (1) all electrical characteristics having room temperature limits are tested during production with t a = t j = 25 c. all hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) device thermal limitations may limit usable range. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: LM5025B
LM5025B snvs354b ? july 2005 ? revised march 2013 www.ti.com electrical characteristics (1) (continued) specifications with standard typeface are for t j = 25 c, and those with boldface type apply over full operating junction temperature range . v in = 48v, v cc = 10v, rt = 26.7k ? , r set = 27.4k ? ) unless otherwise stated symbol parameter conditions min typ max units current limit cs1 prop cs1 delay to output cs1 step from 0 to 0.4v 40 ns time to onset of out transition (90%) c gate = 0 cs2 prop cs2 delay to output cs2 step from 0 to 0.6v 50 ns time to onset of out transition (90%) c gate = 0 cycle by cycle threshold 0.22 0.25 0.28 v voltage (cs1) cycle skip threshold resets ss capacitor; auto 0.45 0.5 0.55 v voltage (cs2) restart leading edge blanking 50 ns time (cs1) cs1 sink impedance cs1 = 0.2v 30 50 ? (clocked) cs1 sink impedance cs1 = 0.3v 55 95 ? (post fault discharge) cs2 sink impedance cs2 = 0.6v 55 95 ? (post fault discharge) cs1 and cs2 leakage cs = cs threshold - 100mv 1 a current soft-start soft-start current source 17 22 27 a normal soft-start current source 0.5 1 1.5 a following a cs2 event oscillator frequency1 t a = 25 c 180 220 200 khz t j = t low to t high 175 225 frequency2 rt = 13.3 k ? t j = t low to t high 360 400 440 khz t j = 0 c to 125 c 364 436 sync threshold 2 v min sync pulse width 100 ns sync frequency range 160 khz pwm comparator delay to output comp step 5v to 0v 40 ns time to onset of out_a transition low maximum duty cycle 1 measured at out_a 73 % maximum duty cycle 2 measured at out_a; 66 71 75 rt = 13.3k comp to pwm offset 0.75 1 1.15 v comp input current comp = 4v, ss open 50 80 a volt x second clamp ramp clamp level delta ramp measured from 2.4 2.5 2.6 v onset of out_a to ramp peak. comp = 5v 6 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM5025B
LM5025B www.ti.com snvs354b ? july 2005 ? revised march 2013 electrical characteristics (1) (continued) specifications with standard typeface are for t j = 25 c, and those with boldface type apply over full operating junction temperature range . v in = 48v, v cc = 10v, rt = 26.7k ? , r set = 27.4k ? ) unless otherwise stated symbol parameter conditions min typ max units uvlo shutdown undervoltage shutdown 2.44 2.5 2.56 v threshold undervoltage shutdown 16 20 24 a hysteresis output section out_a high saturation mos device @ iout = -10ma, 5 10 ? output_a peak current bipolar device @ vcc/2 3 a sink out_a low saturation mos device @ iout = 10ma, 6 9 ? output_a rise time c gate = 2.2nf 20 ns output_a fall time c gate = 2.2nf 15 ns out_b high saturation mos device @ iout = -10ma, 10 20 ? output_b peak current bipolar device @ vcc/2 1 a sink out_b low saturation mos device @ iout = 10ma, 12 18 ? output_b rise time c gate = 1nf 20 ns output_b fall time c gate = 1nf 15 ns output timing control overlap time r set = 38 k ? connected to 75 105 135 ns gnd, 50% to 50% transitions deadtime r set = 29.5 k ? connected to 75 105 135 ns ref, 50% to 50% transitions thermal shutdown t sd thermal shutdown 165 c threshold thermal shutdown 25 c hysteresis thermal resistance ja junction to ambient pw package 125 c/w nhq package 32 c/w jc junction to case pw package 30 c/w nhq package 5 c/w copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: LM5025B
LM5025B snvs354b ? july 2005 ? revised march 2013 www.ti.com typical performance characteristics v cc regulator start-up characteristics, v cc vs vin v cc vs i cc figure 4. figure 5. v ref vs i ref oscillator frequency vs rt figure 6. figure 7. overlap time vs temperature overlap time vs r set r set = 38k figure 8. figure 9. 8 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM5025B -40 25 _ 75 _ 125 temperature ( o c) 80 90 100 110 120 130 140 overlap time (ns) 0 5 10 15 20 25 0 1 2 3 4 5 6 v ref (v) i ref (ma) 0 20 40 60 80 100 120 r set (k : ) 0 50 100 150 200 250 300 350 400 overlap time (ns) 100 1000 frequency (khz) 1 10 100 rt (k : ) 0 2 4 6 8 10 12 14 16 v in (v) 0 2 4 6 8 10 12 14 16 v cc (v) v in v cc 0 5 10 15 20 25 0 2 4 6 8 10 v cc (v) i cc (ma)
LM5025B www.ti.com snvs354b ? july 2005 ? revised march 2013 typical performance characteristics (continued) dead time vs temperature dead time vs r set r set = 29.5k figure 10. figure 11. ss pin current vs temperature figure 12. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: LM5025B -40 25 75 125 temperature ( o c) 14 16 18 20 22 24 26 ss current ( p a) -40 25 75 125 temperature ( o c) 80 90 100 110 120 130 140 deadtime (ns) 0 20 40 60 80 100 120 r set (k : ) 0 50 100 150 200 250 300 350 400 deadtime (ns)
LM5025B snvs354b ? july 2005 ? revised march 2013 www.ti.com detailed operating description the LM5025B is a functional variant of the lm5025 active clamp pwm controller. the functional differences of the LM5025B are as follows: ? the maximum pwm duty cycle is limited to less than 75% to reduce voltage stress on the power mosfets ? the cs2 hiccup mode threshold is increased to 0.5v ? the cs2 filter discharge device is disabled ? the v cc regulator continues to operate when the line uvlo is below the threshold of normal operation ? the v ref regulator is switched off when the line uvlo input falls below the operating threshold ? the internal 5k ? comp pin pull-up resistor is removed the LM5025B pwm controller contains all of the features necessary to implement power converters utilizing the active clamp reset technique. the device can be configured to control either a p-channel clamp switch or an n- channel clamp switch. with the active clamp technique higher efficiencies and greater power densities can be realized compared to conventional catch winding or rdc clamp / reset techniques. two control outputs are provided, the main power switch control (out_a) and the active clamp switch control (out_b). the active clamp output can be configured for either a spefified overlap time (for p-channel switch applications) or a spefified dead time (for n_channel applications). the two internal compound gate drivers parallel both mos and bipolar devices, providing superior gate drive characteristics. this controller is designed for high-speed operation including an oscillator frequency range up to 1mhz and total pwm and current sense propagation delays less than 100ns. the LM5025B includes a high-voltage start-up regulator that operates over a wide input range of 13v to 100v. additional features include: line under voltage lockout (uvlo), softstart, oscillator up/down sync capability, precision reference and thermal shutdown. high voltage start-up regulator the LM5025B contains an internal high voltage start-up regulator that allows the input pin (v in ) to be connected directly to the line voltage. the regulator output is internally current limited to 20ma. when power is applied, the regulator is enabled and sources current into an external capacitor connected to the v cc pin. the recommended capacitance range for the v cc regulator is 0.1 f to 100 f. when the voltage on the v cc pin reaches the regulation point of 7.6v and the internal voltage reference (ref) reaches its regulation point of 5v, the controller outputs are enabled. the outputs will remain enabled until v cc falls below 6.2v or the line under voltage lock out detector indicates that v in is out of range. in typical applications, an auxiliary transformer winding is connected through a diode to the v cc pin. this winding must raise the v cc voltage above 8v to shut off the internal start-up regulator. powering v cc from an auxiliary winding improves efficiency while reducing the controller power dissipation. when the converter auxiliary winding is inactive, external current draw on the v cc line should be limited so the power dissipated in the start-up regulator does not exceed the maximum power dissipation of the controller. an external start-up regulator or other bias rail can be used instead of the internal start-up regulator by connecting the v cc and the v in pins together and feeding the external bias voltage into the two pins. line under-voltage detector the LM5025B contains a line under voltage lock out (uvlo) circuit. an external set-point voltage divider from vin to gnd, sets the operational range of the converter. the divider must be designed such that the voltage at the uvlo pin will be greater than 2.5v when vin is in the desired operating range. if the undervoltage threshold is not met, both outputs and the vref regulator are disabled. the vcc regulator is not disabled by uvlo. uvlo hysteresis is accomplished with an internal 20ua current source that is switched on or off into the impedance of the set-point divider. when the uvlo threshold is exceeded, the current source is activated to instantly raise the voltage at the uvlo pin. when the uvlo pin voltage falls below the 2.5v threshold, the current source is turned off causing the voltage at the uvlo pin to fall. the uvlo pin can also be used to implement a remote enable / disable function. pulling the uvlo pin below the 2.5v threshold disables the pwm outputs. 10 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM5025B
LM5025B www.ti.com snvs354b ? july 2005 ? revised march 2013 pwm outputs the relative phase of the main (out_a) and active clamp outputs (out_b) can be configured for the specific application. for active clamp configurations utilizing a ground referenced p-channel clamp switch, the two outputs should be in phase with the active clamp output overlapping the main output. for active clamp configurations utilizing a high side n-channel switch, the active clamp output should be out of phase with main output and there should be a dead time between the two gate drive pulses. a distinguishing feature of the LM5025B is the ability to accurately configure either dead time (both off) or overlap time (both on) of the gate driver outputs. the overlap / deadtime magnitude is controlled by the resistor value connected to the time pin of the controller. the opposite end of the resistor can be connected to either ref for deadtime control or gnd for overlap control. the internal configuration detector senses the connection and configures the phase relationship of the main and active clamp outputs. the magnitude of the overlap/dead time can be calculated as follows: overlap time (ns) = 2.8 x r set - 1.2 dead time (ns) = 2.9 x r set +20 r set in k ? , time in ns figure 13. compound gate drivers the LM5025B contains two unique compound gate drivers, which parallel both mos and bipolar devices to provide high drive current throughout the entire switching event. the bipolar device provides most of the drive current capability and provides a relatively constant sink current which is ideal for driving large power mosfets. as the switching event nears conclusion and the bipolar device saturates, the internal mos device continues to provide a low impedance to compete the switching event. during turn-off at the miller plateau region, typically around 2v - 3v, is where gate driver current capability is needed most. the resistive characteristics of all mos gate drivers are adequate for turn-on since the supply to output voltage differential is fairly large at the miller region. during turn-off however, the voltage differential is small and the current source characteristic of the bipolar gate driver is beneficial to provide fast drive capability. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: LM5025B out_a out_b out_a out_b k1 * r set n-channel active clamp (r set to ref) p-channel active clamp (r set to gnd) k2 * r set k1 * r set k2 * r set
LM5025B snvs354b ? july 2005 ? revised march 2013 www.ti.com pwm comparator the pwm comparator compares the ramp signal (ramp) to the loop error signal (comp). this comparator is optimized for speed in order to achieve minimum controllable duty cycles. the comp pin is a high impedance comparator input. if the opto coupler is connected between the comp pin and ground, then a pull-up resistor must be added between comp and ref to bias the opto coupler transistor. the comparator polarity is such that 0v on the comp pin will produce a zero duty cycle on both gate driver outputs. volt x second clamp the volt x second clamp comparator compares the ramp signal (ramp) to a fixed 2.5v reference. by proper selection of rff and cff, the maximum on time of the main switch can be set to the desired duration. the on time set by volt x second clamp varies inversely with the line voltage because the ramp capacitor is charged by a resistor connected to vin while the threshold of the clamp is a fixed voltage (2.5v). an example will illustrate the use of the volt x second clamp comparator to achieve a 50% duty cycle limit, at 200khz, at a 48v line input: a 50% duty cycle at a 200khz requires a 2.5 s of on time. at 48v input the volt x second product is 120v- s (48v x 2.5 s). to achieve this clamp level choose rff and cff using the following equation: r ff x c ff = v in x t on / 2.5v = (1) 48v x 2.5 s / 2.5v = 48 s (2) select c ff = 470pf. r ff = 102k ? . the recommended capacitor value range for c ff is 100pf to 1000pf. the c ff ramp capacitor is discharged at the conclusion of every cycle by an internal discharge switch controlled by either the internal clock or by the volt x second clamp comparator, whichever event occurs first. maximum duty cycle at low line input voltages, the volt x second clamp will not limit the maximum pwm duty cycle because the ramp signal does not charge to the 2.5v threshold voltage within the period of the pwm clock. in this case, the maximum duty cycle is determined by the internal pwm clock and the output overlap or deadtime programmed by the resistor rset connected to the time pin. referring to figure 13 , the initial transition of out_b corresponds to the leading edge of the pwm clock. the leading edge of out_a is delayed with respect to out_b by the overlap time which is determined by the time pin resistor (k1 x rset) when operating at maximum duty cycle, the trailing edge of out_a corresponds to the trailing edge of the pwm clock. the duty cycle at out_a is therefore always less than the duty cycle of the clock. the internal clock of the LM5025B operates at a nominal duty cycle of 75%. if the clock frequency is 400khz and the overlap time is set to 100ns, then the maximum pwm duty cycle will be: max duty cycle = 75% - 100ns x 400khz = 71% (3) 12 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM5025B v cc pgnd cntrl out
LM5025B www.ti.com snvs354b ? july 2005 ? revised march 2013 current limit the LM5025B contains two modes of over-current protection. if the sense voltage at the cs1 input exceeds 0.25v the present power cycle is terminated (cycle-by-cycle current limit). if the sense voltage at the cs2 input exceeds 0.5v, the controller will terminate the present cycle, discharge the softstart capacitor and reduce the softstart current source to 1 a. the softstart (ss) capacitor is released after being fully discharged and slowly charges with a 1 a current source. when the voltage at the ss pin reaches approximately 1v, the pwm comparator will produce the first output pulse at out_a. after the first pulse occurs, the softstart current source will revert to the normal 20 a level. fully discharging and then slowly charging the ss capacitor protects a continuously over-loaded converter with a low duty cycle hiccup mode. these two modes of over-current protection allow the user great flexibility to configure the system behavior in over-load conditions. if it is desired for the system to act as a current source during an over-load, then the cs1 cycle-by-cycle current limiting should be used. in this case the current sense signal should be applied to the cs1 input and the cs2 input should be grounded. if during an overload condition it is desired for the system to briefly shutdown, followed by softstart retry, then the cs2 hiccup current limiting mode should be used. in this case the current sense signal should be applied to the cs2 input and the cs1 input should be grounded. this shutdown / soft-start retry will repeat indefinitely while the over-load condition remains. the hiccup mode will greatly reduce the thermal stresses to the system during heavy overloads. the cycle-by-cycle mode will have higher system thermal dissipations during heavy overloads, but provides the advantage of continuous operation for short duration overload conditions. it is possible to utilize both over-current modes concurrently, whereby momentary overload conditions activate the cs1 cycle-by-cycle mode while prolonged overloading activates the cs2 hiccup mode. generally the cs1 input will always be configured to monitor the main switch fet current each cycle. the cs2 input can be configured in several different ways depending upon the system requirements. a) the cs2 input can also be set to monitor the main switch fet current except scaled to a higher threshold than cs1 b) an external over-current timer can be configured which trips after a pre-determined over-current time, driving the cs2 input high, initiating a hiccup event. c) in a closed loop voltage regulaton system, the comp input will rise to saturation when the cycle-by-cycle current limit is active. an external filter/delay timer and voltage divider can be configured between the comp pin and the cs2 pin to scale and delay the comp voltage. if the cs2 pin voltage reaches 0.5v a hiccup event will initiate. a small rc filter, located near the controller, is recommended for each of the cs pins. the cs1 input has an internal fet which discharges the current sense filter capacitor at the conclusion of every cycle, to improve dynamic performance. this same fet remains on an additional 50ns at the start of each main switch cycle to attenuate the leading edge spike in the current sense signal. the cs2 discharge fet only operates following a cs2 event, uvlo and thermal shutdown. the LM5025B cs comparators are very fast and may respond to short duration noise pulses. layout considerations are critical for the current sense filter and sense resistor. the capacitor associated with the cs filter must be placed very close to the device and connected directly to the pins of the ic (cs and gnd). if a current sense transformer is used, both leads of the transformer secondary should be routed to the filter network , which should be located close to the ic. if a sense resistor in the source of the main switch mosfet is used for current sensing, a low inductance type of resistor is required. when designing with a current sense resistor, all of the noise sensitive low power ground connections should be connected together near the ic gnd and a single connection should be made to the power ground (sense resistor ground point). copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: LM5025B
LM5025B snvs354b ? july 2005 ? revised march 2013 www.ti.com oscillator and sync capability the LM5025B oscillator is set by a single external resistor connected between the rt pin and gnd. to set a desired oscillator frequency (f), the necessary rt resistor can be calculated from: rt = (4960/f) 1.02 where ? f is in khz and rt in k ? . (4) the rt resistor should be located very close to the device and connected directly to the pins of the ic (rt and gnd). a unique feature of LM5025B is the ability to synchronize the oscillator to an external clock with a frequency that is either higher or lower than the frequency of the internal oscillator. the lower frequency sync frequency range is 80% of the free running internal oscillator frequency. there is no constraint on the maximum sync frequency. a minimum pulse width of 100ns is required for the synchronization clock. if the synchronization feature is not required, the sync pin should be connected to gnd to prevent any abnormal interference. the internal oscillator can be completely disabled by connecting the rt pin to ref. once disabled, the sync signal will act directly as the master clock for the controller. both the frequency and the maximum duty cycle of the pwm controller can be controlled by the sync signal (within the limitations of the volt x second clamp). the maximum duty cycle (d) will be (1-d) of the sync signal. feed-forward ramp an external resistor (r ff ) and capacitor (c ff ) connected to v in and gnd are required to create the pwm ramp signal. the slope of the signal at the ramp pin will vary in proportion to the input line voltage. this varying slope provides line feedforward information necessary to improve line transient response with voltage mode control. the ramp signal is compared to the error signal at the comp pin by the pulse width modulator comparator to control the duty cycle of the main switch output. the volt x second clamp comparator also monitors the ramp pin and if the ramp amplitude exceeds 2.5v, the present cycle is terminated. the ramp signal is reset to gnd at the end of each cycle by either the internal clock or the volt x second comparator, which ever occurs first. soft-start the soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. at power on, a 20 a current is sourced out of the soft-start pin (ss) into an external capacitor. the capacitor voltage will ramp up slowly and will limit the comp pin voltage and therefore the pwm duty cycle. in the event of a fault as determined by v cc undervoltage, line undervoltage (uvlo) or second level current limit, the output gate drivers are disabled and the soft-start capacitor is fully discharged. when the fault condition is no longer present a soft-start sequence will be initiated. following a second level current limit detection (cs2), the soft-start current source is reduced to 1 a until the first output pulse is generated by the pwm comparator. the current source returns to the nominal 20 a level after the first output pulse (~1v at the ss pin). 14 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM5025B cs2 ss 1 p a 20 p a out_a 0.5v overload cool down restart
LM5025B www.ti.com snvs354b ? july 2005 ? revised march 2013 the soft-start circuit controls the comp pin voltage through a unity gain amplifier with an open drain (sink only) output. if the ss pin voltage is less than the pwm control signal applied to the comp pin, this amplifier will sink current from the external pull-up connected to the comp pin to force the comp voltage to follow the soft-start capacitor ramp. when the soft-start capacitor charges to a voltage that is greater than the control voltage applied to the comp pin, the soft-start amplifier automatically disengages, allowing closed loop control of the pwm duty cycle. the soft-start amplifier output stage is capable of sinking up to 5ma. external pull-up circuits connected to the comp pin must limit the current into the pin to a value less than 5ma. thermal protection internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. when activated, typically at 165 c, the controller is forced into a low power standby state with the output drivers and the bias regulator disabled. the device will restart after the thermal hysteresis (typically 25 c). during a restart after thermal shutdown, the soft-start capacitor will be fully discharged and then charged in the low current mode (1 a) similar to a second level current limit event. the thermal protection feature is provided to prevent catastrophic failures from accidental device overheating. application circuit: input 36-78v, output 3.3v, 30a copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: LM5025B
LM5025B snvs354b ? july 2005 ? revised march 2013 www.ti.com revision history changes from revision a (march 2013) to revision b page ? changed layout of national data sheet to ti format .......................................................................................................... 15 16 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM5025B
package option addendum www.ti.com 2-oct-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples LM5025Bmtc/nopb active tssop pw 16 92 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 l5025b mtc LM5025Bmtcx/nopb active tssop pw 16 2500 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 l5025b mtc LM5025Bsd/nopb active wson nhq 16 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 5025bsd (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 2-oct-2014 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant LM5025Bmtcx/nopb tssop pw 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 q1 LM5025Bsd/nopb wson nhq 16 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 q1 package materials information www.ti.com 28-jul-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) LM5025Bmtcx/nopb tssop pw 16 2500 367.0 367.0 35.0 LM5025Bsd/nopb wson nhq 16 1000 210.0 185.0 35.0 package materials information www.ti.com 28-jul-2016 pack materials-page 2

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